SP3243 PDF

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The "U" and "H" series are optimized for high speed with data rates up to 1Mbps, easily meeting the demands of high speed RS applications.

The SP series uses an internal high-efficiency, charge-pump power supply that requires only 0. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.

Continuous Storage Temperature Skew ns 50 0 0 T1 at Kbps T2 at Transmitter Skew VS. Transmitter Output Voltage VS.

Supply Current VS. Slew Rate VS. Apply logic LOW for normal operation. C1- Negative terminal of the voltage doubler charge-pump capacitor. C2- Negative terminal of the inverting charge-pump capacitor. V- Regulated RS receiver input. Non-inverting receiver-2 output, active in shutdown. RS driver output. NC No Connection Table 1. The SPEU devices can operate at a data rate of kbps fully loaded. The SP includes one complementary always-active receiver that can monitor an external device such as a modem in shutdown.

The SP series is an ideal choice for power sensitive designs. In many portable or hand-held applications, an RS cable can be disconnected or a connected peripheral can be turned off.

Under these conditions, the internal charge pump and the drivers will be shut down. Otherwise, the system automatically comes online. This feature allows design engineers to address power saving concerns without major design changes. Drivers 2. Receivers 3. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. The drivers have a minimum data rate of kbps EB or kbps EU fully loaded. Figure 17 shows a loopback test circuit used to test the RS Drivers.

Figure 18 shows the test results where one driver was active at 1Mbps and all three drivers loaded with an RS receiver in parallel with a pF capacitor. Figure 19 Figure Loopback Test Circuit for RS Driver Data Transmission Rates shows the test results of the loopback circuit with all drivers active at kbps with typical RS loads in parallel with pF capacitors. During the shutdown, the receivers will continue to be active.

The Figure Loopback Test results at 1Mbps Figure Copyright Sipex Corporation truth table logic of the SP driver and receiver outputs can be found in Table 2. R2OUT is an extra output that remains active and monitors activity while the other receiver outputs are forced into high impedance.

Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of mV. This ensures that the receiver is virtually immune to noisy transmission lines.

Charge Pump The charge pump is a Sipex—patented design U. The charge pump still requires four external capacitors, but uses a four—phase voltage shifting technique to attain symmetrical 5. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.

This is important to maintain compliant RS levels regardless of power supply fluctuations. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5. If the output voltages exceed a magnitude of 5. This oscillator controls the four phases of the voltage shifting.

A description of each phase follows. Phase 1 — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are then switched transferred to tCion2iG—t. This transfers a negative generated voltage to C4. This generated voltage is regulated to a minimum voltage of Phase 3 — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces —VCC in the negative terminal of C1, which side of capacitor C2.

At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. The clock rate for the charge pump typically operates at greater than kHz.

The external capacitors can be as low as 0. Either polarized or non polarized capacitors may be used. If polarized capacitors are used they should be oriented as shown in the Typical Operating Circuit. The charge pump operates with 0. For other supply voltages, see the table for required capacitor values. Do not use values smaller than those listed.

Increasing the capacitor values e. Once active, the device is enabled until there is no activity on the receiver inputs. The receiver reduces ripple on the transmitter outputs and may slightly reduce power consumption.

For best charge pump efficiency locate the charge pump and bypass capacitors as close as possible to the IC. Surface mount capacitors are best for this purpose. Using capacitors with lower equivalent series resistance ESR and selfinductance, along with minimizing parasitic PCB trace inductance will optimize charge pump operation.

Designers are also advised to consider that capacitor values may shift over time and operating temperature. When this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standy mode.

Timing Waveforms The first stage, shown in Figure 28, detects an inactive input. This circuit is duplicated for each of the other receivers. This can commonly occur in hand-held or portable applications where the RS cable is disconnected or the RS drivers of the connected peripheral are turned off.

The truth table logic of the SP driver and receiver outputs can be found in Table 2. This pin goes to a logic HIGH when the external transmitters are enabled and the cable is connected. When the SP devices are shut down, the charge pumps are turned off. The decay time will depend on the size of capacitors used for the charge pump. SP Driver Output Voltages vs. Load Current per Transmitter The SP driver outputs are able to maintain voltage under loading of up to 2.

Received Line Signal Detector 2. Received Data 3. Transmitted Data 4. Data Terminal Ready 5. Signal Ground Common 6. DCE Ready 7.

Request to Send 8. Clear to Send 9. Ring Indicator Figure The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The simulation is performed by using a test model as shown in Figure For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence.

The premise with IEC is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The test circuit for IEC is shown on Figure This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel.

The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current.

For example, the rise time of the discharge current varies with the approach speed. This method was devised to reduce the unpredictability of the ESD arc.


SP3243 PDF



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