DS2401 PDF

The initialization sequence consists of a reset pulse transmitted by the bus master followed by a Presence Pulse s transmitted by the slave s. The Presence Pulse lets the bus master know that the DS is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. All ROM function commands are 8 bits long.

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DESCRIPTION The DS enhanced silicon serial number is a low-cost, electronic registration number that provides an absolutely unique identity which can be determined with a minimal electronic interface typically, a single port pin of a microcontroller.

Data is transferred serially via the 1-Wire protocol that requires only a single data lead and a ground return. Power for reading and writing the device is derived from the data line itself with no need for an external power source. The is an upgrade to the DS The DS is fully reverse-compatible with the DS but provides the additional multi-drop capability that enables many devices to reside on a single data line.

The familiar SOT or TSOC package provides a co mpact enclosure that allows standard assembly equipment to handle the device easily. The bit serial number, 8-bit family code and 8-bit CRC are retrieved using the Maxim 1-Wire protocol.

This protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. All data is read and written least significant bit first. The 1-Wire bus is a system which has a single bus master system and one or more slaves.

In all instances, the is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling signal type and timing. The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time.

To facilitate this, each device attached to the 1-Wire bus must have an open-drain connection or 3-state outputs. The is an open-drain part with an internal circuit equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together.

The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3. The value of the pullup resistor should be approximately 5k for short line lengths. A multidrop bus consists a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of The idle state for the 1-Wire bus is high.

If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Note: Depending on the 1-Wire communication speed and the bus load characteristics, the optimal pullup resistor RPU value will be in the to 5k range.


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